Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external programmable read only memory (“PROM”) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include these exemplary devices, as well as encompassing devices that are only partially programmable
An incoming information stream (“data stream”), which may include control information and data, to an FPGA may be at a data rate that is higher than that which may be processed by FPGA programmable circuitry (“FPGA fabric”). The FPGA fabric can include block random access memories (BRAMs), that are dual ported memory blocks, such as those found in the Virtex II FPGA chip from Xilinx, Inc. of San Jose, Calif. For example, for a high-bandwidth application, memory read or write cycle time of BRAMs of FPGA fabric may be insufficient to process each incoming word of a data stream sequentially. To address this imbalance between data rate of an incoming data stream and data rate which may be handled by BRAMs, one may write and read multiple words of the data stream into and out of BRAMs configured to be N words wide, for N a positive integer.
Conventionally, multi-word data is written to and retrieved from N word wide queues. Accessing N words at a time from the same physical address is known as single address pointer access. BRAMs of an FPGA may be configured to provide one or more circular queues to receive an incoming data stream. However, configuring BRAMs as a circular queue with a width of N words has a drawback when a packet or cell boundary is not an integer multiple of integer N. In reads or writes, where a packet or cell boundary is not an integer multiple of integer N, a starting point (“word zero”) of a packet or cell may appear in any of N possible word locations of such a memory configuration. In other words, a packet or cell word zero may not be aligned to a physical address boundary. Because a packet or cell starting point may be in any of the N possible word locations, this randomness complicates reconstruction of a packet or a cell.
Others have addressed this data alignment issue by implementing what is known as “barrel shifting.” However, implementing a barrel shifter in an FPGA may consume a significant amount of resources and power.
Accordingly, it would be desirable and useful to provide means by which packets or cells may be accessed where a first word of a retrieved packet or cell appears in a same location regardless of where such word originated in a physical memory space.